Memory array having 2T memory cells

ABSTRACT

The present invention relates to a memory array having a plurality of memory cells. In order to combine the compactness of DRAM with the speed and uncomplicated processing profits of SRAM the present invention proposes a memory array having a plurality of memory cells each comprising:—a storage transistor having a drain coupled to a word-line of said array, a source coupled to a bit-line of said array and a gate, and—a control transistor having a drain coupled to the gate of said storage transistor, a source coupled to said bit-line and a gate coupled to said word-line.

The invention relates to a memory array having a plurality of memorycells.

There are many different memory cells known for use in a semiconductormemory array. A widely known and used type of a DRAM memory cellcomprises a single transistor and a capacitor coupled to the drain ofsaid transistor. Because of the parasitic capacitance on a bit-line towhich the source of said capacitor is coupled such a memory cell needs alarge capacitor for robust operation. Further, since the read-out isdestructive a read operation has to be followed by a rewrite operation.

A memory cell having three transistors is known from H. Veendrick,“Deep-Submicron CMOS ICs”, Kluwer Academic Publishers, 2^(nd) Englishedition, 2000, pp. 272. Instead of one word-line such a cell has twoword-specific control lines. Since the cell requires 3 transistors, inpractice this results in an insufficient silicon area reduction comparedto SRAM solutions.

In general, DRAM memory cells enable a compact memory solution. On theother hand, SRAM memory cells do not require any additional mask stepson top of the default process which saves both costs and time-to-market.Further, SRAM is usually faster than DRAM.

It is therefore an object of the present invention to provide a memoryarray having a plurality of memory cells which approaches thecompactness of DRAM and combines this with the speed and uncomplicatedprocessing profits of SRAM.

This object is achieved according to the present invention by a memoryarray as claimed in claim 1, according to which each memory cellcomprises:

-   -   a storage transistor having a drain coupled to a word-line of        said array, a source coupled to a bit-line of said array and a        gate, and    -   a control transistor having a drain coupled to the gate of said        storage transistor, a source coupled to said bit-line and a gate        coupled to said word-line.

With the memory cells of the memory array according to the presentinvention the load is stored at the gate of the storage transistor. Asfunction of the momentary capacitance at the gate the load results in astorage voltage. The storage transistor can be enabled to pull a currentin a read-mode. The control transistor is used to enable or disable theprogramming of the storage voltage. The present invention thus providesa solution which combines both the advantages of a 1T DRAM cell and a 3Tcell as described above, i.e. it provides a very small cell having anon-destructive read-out. Further, the read-out is potentially fasterthan a conventional DRAM cell as the memory cell according to thepresent invention has a built-in amplification and since the restorecycle can be omitted.

Preferred advantageous embodiments of the present invention are definedin the dependent claims. According to one aspect of the invention meansare provided for applying a word-line voltage to said word-line and/or abit-line voltage to said bit-line, and further control means forcontrolling said word-line voltage so as to define three static statesof a memory cell. Such static states are, as defined further in claim 3,a pull state, a store state and a write state. The word-line is used tocontrol read, write and store operation modes of the memory cell, whilea bit-line voltage is used to determine the storage voltage as a resultof a write operation.

The 2T memory cell used in the memory array according to the presentinvention can be in such different static states. The basic operationsneeded for data-manipulation, like a write operation and aread-operation, require transitions between such static states. Thoseoperations are referred to as “dynamic operations” and are controlled bysaid control means by controlling the word-line voltage. Preferredembodiments defining control means for controlling such dynamicoperations are defined in claims 4 and 5.

According to another preferred embodiment low-leakage MOS transistorsare used as storage transistor and control transistor of said memorycells. In still another preferred embodiment, NMOST or PMOST memorycells are used.

According to another aspect an extra capacitance can be provided on thegate of the storage transistor against ground. At the expense of siliconarea improved refresh times can thus be implemented.

The invention will now be explained in more detail with reference to thedrawings, in which

FIG. 1 shows the layout of a known 1T memory cell,

FIG. 2 shows the layout of a known 3T memory cell,

FIG. 3 shows the NMOST layout of a memory cell according to the presentinvention,

FIG. 4 shows the PMOST layout of a memory cell according to the presentinvention,

FIG. 5 shows a general layout of a memory array,

FIG. 6 shows a diagram illustrating the different static states anddynamic operations according to the present invention, and

FIG. 7 shows another embodiment of a memory cell according to thepresent invention.

FIG. 1 shows the layout of a conventional 1T (one-transistor) DRAMmemory cell 10. Said memory cell 10 comprises a single transistor Thaving a drain 11, a gate 12 and a source 13. Further, said memory cell10 comprises a capacitor C the first electrode of which is coupled tothe drain 11 and the second electrode of which is coupled to an inputterminal 14 for supplying an input voltage such as a ground voltage or asupply voltage (particularly a supply voltage divided by a factor of 2).The gate 12 is connected to a word-line WL for applying a word-linevoltage Vword; the source 13 is connected to a bit-line BL for applyinga bit-line voltage Vbit. A storage voltage Vst is provided at drain 11.

Such a memory cell 10 needs a large capacitor C for robust operation,because of the parasitic capacitance on the bit-line BL during a readoperation. The active read-out of the 2T cell results in the effect ofan amplified capacitor, thus enabling a faster read operation. Further,additional mask steps are required to manufacture area-efficient trenchcapacitors. A hierarchical breakdown of sense-amplifiers is required forrobust read-out, adding up to the average storage cell area. A furtherdisadvantage of this memory cell is that a read operation has to befollowed by a rewrite, as the read-out is destructive.

The layout of a known 3T (threee-transistor) memory cell 20 is shown inFIG. 2. This memory cell 20 comprises three transistors T1, T2, T3. Thedrain 21 of the first transistor T1 and the source 29 of the thirdtransistor T3 are connected to a bit-line BL to which a bit-line voltageVbit can be applied. The gate 22 of the first transistor T1 is coupledto a first control-line CL1 to which a first control voltage Vread canbe applied. The source 23 of the first transistor T1 is connected to thedrain 24 of the second transistor T2. The gate 25 of the secondtransistor T2 is connected to the drain 27 of the third transistor T3.The source 26 of the second transistor T2 is connected to a voltageinput terminal 20 for supply of an input voltage. The gate of the thirdtransistor T3 is connected to a second control line CL2 to which asecond control voltage Vwrite can be applied. A storage voltage Vst isprovided at gate 25.

Thus, as shown in FIG. 2, instead of one word-line as in the 1T memorycell shown in FIG. 1, the cell 20 has two word-specific control lines,i.e. a read and a write line that are used to enable read and writeoperation. Since in total three transistors are required, in practicethis results in insufficient silicon area reduction compared to SRAMsolutions.

FIG. 3 shows the layout of a first embodiment of a 2T (two-transistor)memory cell 30 according to the present invention. Shown is an NMOSTlayout. The memory cell 30 comprises two transistors, a storagetransistor Ts and a control transistor Tc. The drain 31 of the storagetransistor Ts is coupled to a word-line WL. The gate 32 of the storagetransistor Ts is coupled to the drain 34 of the control transistor Tc.The source 33 of the storage transistor Ts is coupled to a bit-line BL.The gate 35 of the control transistor Tc is also coupled to the wordlineWL. The source 36 of the control transistor Tc is coupled to the bitlineBL.

The load in this memory cell 30 is stored at the gate node 32 of thestorage transistor Ts. As function of the momentary capacitance at thegate node 32 the load results in a storage voltage Vst at said gate node32. The storage transistor Ts can be enabled to pull a current inread-mode.

The control transistor Tc is provided for enabling or disabling theprogramming of said storage voltage Vst. A word-line voltage Vword isapplied on the word-line WL. The word-line WL is thus used to controlthe read, write and store operation modes of the memory cell 30.Further, a bit-line voltage Vbit is applied on the bit-line BL. Thisbit-line voltage determines the storage voltage Vst as a result of awrite operation as will be explained below.

Another embodiment of a memory cell 30′ according to the presentinvention is shown in FIG. 4. Therein a PMOST version is shown. However,the general layout and the general function is identical to the memorycell 30 shown in FIG. 3.

The layout of a memory array comprising a plurality of preferablyindentical memory cells arranged in rows and columns is shown in FIG. 5.As shown, there are K rows with associated word-lines WL1, WL2, . . . ,WLK. Each row comprises N memory cells connected to the word-line. Anindividual word-line voltage Vword can be applied to the word-line. TheN memory cells of one row form one word W. Further, K columns of memorycells are formed, the memory cells of each column connected to aspecific bit-line BL of N bit-lines BL0, BL1, . . . , BLN-1. To each ofsaid bit-lines an individual bit-line voltage Vbit can be applied.

The operating principle will be explained using the embodiment of theNMOST variant of the 2T memory cell as shown in FIG. 3 and as it is usedfor a digital application. However, it should be noted, that the memorycell according to the present invention is capable of storing a loadthat is within a particular range. This enables digital, multi-valued oranalogue storage, or any combination of these storage principles.

The 2T memory cell according to the invention can be in several statesthat need a distinct description. These are referred to as the “staticstates”. The basic operations needed for data-manipulation, like “write1” and “read”, require transitions between static states. Theseoperations are referred to as “dynamic operations”. There are threestatic states that can be defined with the word-line voltage Vword andthe storage voltage Vst. These states are:

-   a) pull-state: Vss<Vword<Vst−Vt (Vss=ground voltage; Vt=threshold    voltage). In this state a current is pulled from the bit-line    through the storage transistor Ts into the word-line. The control    transistor Tc is “off”.-   b) store-state: Vst−Vt<Vword<Vst+Vt. Both the storage transistor Ts    and the control transistor Tc are “off”; the storage voltage Vst    remains.-   c) write-state: Vst+Vt<Vword<Vdd. The control transistor Tc is    “open” and the storage voltage Vst equals the bit-line voltage Vbit.

FIG. 6 shows the transitions between the static states that are requiredto carry out the dynamic operations:

-   1. Read-operation: Initially, the memory cell is in the store-state    S1. By decreasing the word-line voltage Vword from the store level    Vstore to the read level Vread the memory cell can change into the    pull-state S3 or store/pull state S2. For instance, Vread can equal    Vss. Whether the change of static state occurs, depends on the    storage voltage value Vst. After comparison of the current through    the bit-line with a reference current, the word-line voltage Vword    sweeps back to Vstore and the memory cell changes back into the    store state S1.

a) read “0” (transition D12): the memory cell remains in the store-stateand no current flows through the bit-line. This is interpreted as adigital “0”. It is also possible to move the memory cell into thepull-state to pull a current smaller than the reference current.

b) read “1” (transition D13): the memory cell has transferred to thepull-state S3. A current that is larger than the reference current ispulled from the bit-line. This is interpreted as a digital “1”.

-   2. Write operation: initially the memory cell is in the store-state    S1. By increasing the word-line voltage Vword from the store level    Vstore (state S4) to the write level Vwrite, the memory cell can    change to the write state S5 (transition D45). For instance, Vwrite    can equal Vdd. The storage voltage Vst equals Vbit. After that, the    word-line voltage Vword sweeps back to the Vstore value (transition    D51) and the memory cell changes back into the store state S1. In    principle, the storage voltage Vst becomes the minimum of Vbit or    the difference of Vdd and Vt, i.e. Vst becomes min (Vbit, Vdd−Vt).

a) write “1” (transitions D14, D45, D51): offer Vbit=V1, V1 equals e.g.Vdd.

b) write “0” (transitions D16, D67, D71): offer Vbit=V0 (states S6, S7),V0 large enough to prevent leakage through the control transistor Tc innon-selected words.

-   3. Refresh operation: this operation is the sequence of a read and a    write (rewrite) operation.

FIG. 7 shows another embodiment of a 2T memory cell 30″ according to thepresent invention which is substantially identical to the layout of thememory cell 30 shown in FIG. 3. The only difference is that an extracapacitance C1 is implemented on the gate 32 of the storage transistorTs, the other electrode of the capacitance C1 being connected to theground voltage Vss, i.e. between Vst and Vss. This capacitance C1 isused to improve the refresh times.

Compared to the known solutions the 2T memory cell according to thepresent invention based on DRAM has a bit-density comparable toconventional DRAM solutions. The memory cell according to the presentinvention can be produced with a default process flow. A conventionalDRAM requires an overhead of additional mask steps. The 2T memory cellaccording to the present invention based on DRAM enables significantsavings on the processing costs and improved time-to-market. Further,the 2T memory cell according to the present invention based on DRAM canbe combined with flash memory. Conventionally, flash memory processingcould not be combined with the process steps for conventional DRAMmemory. Usually SRAM memory is used by lack of an alternative solution.The 2T memory cell according to the present invention is a cheapalternative for SRAM in such combined flash memory ICs.

The 2T memory cell based on DRAM according to the present inventionimplies two major benefits. First, the read-out is non-destructive.Second, the built-in amplification relaxes the requirements for theperipheral circuitry for the sensing during read-out. This saves siliconarea occupied by sense-amplifiers.

The invention is generally based on the insight to use (a part of) thespan of the gate-voltage where MOS transistor is “off” to control otherprocessing. According to the invention the lower part of the “off”region of the gate voltage of an NMOS transistor has been used to inducethe floating of a current in case a “1” was programmed in the 2T memorycell according to the invention.

1. A memory array having a plurality of memory cells each comprising: astorage transistor having a drain coupled to a word-line of said array,a source coupled to a bit-line of said array and a gate, and a controltransistor having a drain coupled to the gate of said storagetransistor, a source coupled to said bit-line and a gate coupled to saidword-line.
 2. The memory array of claim 1, further comprising means forapplying a word-line voltage to said word-line and/or a bit-line voltageto said bit-line and control means for controlling said word-linevoltage so as to define three static states of a memory cell.
 3. Thememory array of claim 2, wherein said control means are adapted fordefining a pull state by controlling said word-line voltage to be largerthan a ground voltage and to be smaller than a difference of a storagevoltage provided at the gate of said storage transistor and a thresholdvoltage of said transistors, a store state by controlling said word-linevoltage to be larger than a difference of said storage voltage and saidthreshold voltage and to be smaller than a sum of said storage voltageand said threshold voltage, and a write state by controlling saidword-line voltage to be larger than a sum of said storage voltage andsaid threshold voltage and to be smaller than a supply voltage.
 4. Thememory array of claim 3, wherein said control means are adapted forcontrolling said word-line voltage so as to define dynamic operations,in particular a read and a write operation, as transitions between twostatic states, wherein a read operation is defined as a transitionbetween said store state and said pull state, and a write operation isdefined as a transition between said store state and said write state.5. The memory array of claim 4, wherein said control means are adaptedto decrease said word-line voltage from a store-level to a read-level tocarry out a read operation and to increase said word-line voltage from astore-level to a write-level to carry out a write operation.
 6. Thememory array of claim 1, wherein low-leakage MOS transistors are used asstorage transistor and control transistor.
 7. The memory array of claim1, wherein NMOST or PMOST memory cells are used.
 8. The memory array ofclaim 1, wherein each memory cell comprises further comprises acapacitance coupled between the gate of said storage transistor andground.
 9. A memory cell comprising: a first transistor, coupled toreceive data from a source and to a first command line, that stores thedata on a gate of the first transistor; a second transistor, coupled tothe first transistor and a second command line, that controls the readand write function of the first transistor; and wherein the memory celldoes not contain more than two transistors.
 10. The memory cell of claim9 wherein the data is stored within momentary capacitance on the gate ofthe first transistor.
 11. The memory cell of claim 9 wherein the firstcommand line sets a mode for the first transistor.
 12. The memory cellof claim 9 wherein the second command line provides enable and disablecommands.